The present invention relates to a technique for predicting aging property deterioration of a large scale semiconductor integrated circuit (hereinafter, abbreviated as LSI) caused by the hot carrier phenomenon (deterioration) or the like, and obtaining a suitable aging deterioration margin amount as an allowance to be made at time of designing LSIs or inspecting LSIs.
In recent years, LSIs have reached the point where several ten million or more MOS transistors are integrated to realize various functions on one chip. In such LSIs, it is necessary that a tolerance, that is, a margin amount is included for various properties in the design stage so that the LSIs can operate normally, even if the supply voltage or the temperature used are varied, or the properties are not uniform. In the following description, delay of signals is used as an example of the margin amount.
In general, a LSI can be disintegrated into a plurality of basic units, each of which includes a certain number of stages of circuits 22 (N stages in FIG. 1) between, for example, flip-flops 21, 21, that is, a plurality of signal paths 20, as shown in FIG. 1. Each of the circuits 22 includes logic circuits and wiring connecting these logic circuits in many cases. The delay of a signal when the signal propagates through a series of circuits 22 of the signal path 20 is required to be within a predetermined period of time, that is, a cycle time (the inverted number of the operation frequency or the clock frequency in many cases) of a clock signal 23 supplied to the flip-flops 21, 21, as shown in the following equation (1).
t cyclexe2x89xa7xcexa3ti+K(i=1 to N)xe2x80x83xe2x80x83(1) 
where t cycle is a cycle time, which is a design target property, xcexa3ti is the total of signal propagation delay between input and output terminals of each circuit i (22) between the flip-flops 21, that is, a signal path delay in the LSI, and K is the sum of the setup time of the flip-flops 21 and the skew of the clock signal 23.
The maximum value (the worst value) of the xcexa3ti can be obtained by simulation of delay variation in a circuit operation, or a method of using derating factors, which are coefficients that represent the influence of various delay variation factors, is known as an approach for saving work load for design. More specifically, this is a method of designing by roughly estimating the worst conditions from a typical delay, as shown in the following equation (2).
t worst=t typxc3x97Pxc3x97Vxc3x97Txe2x80x83xe2x80x83(2) 
where t worst is the maximum value (the worst value) of each signal path delay, t typ is a typical value of each signal path delay, P is a delay variation coefficient in accordance with production deviation, V is a delay variation coefficient in accordance with the amount of a supply voltage variation width, and T is a delay variation coefficient in accordance with the amount of a temperature variation width. The difference between the t worst and the t typ is a margin amount for the delay variation to be considered.
The typical value t typ of the signal path delay can be obtained by a quite smaller scale simulation than by a simulation where the maximum value of the delay variation is obtained. If the typical values of all the signal path delays of the LSI are obtained, the worst value can be obtained efficiently, simply by multiplying these typical values by the derating factors P, V, and T. Such an approach is more often used for LSI design for specific applications such as ASIC than for the types for which a custom design is often used, such as microprocessors.
LSIs have their lifetime as other products, and disorder or malfunction occurs in a certain period of operation time after production. As the main causes of disorder or malfunction, property deterioration due to the hot carrier phenomenon, or breakage of wiring or short-circuit due to electromigration is known. In particular, in recent LSIs, miniaturization of transistors has been rapidly developed with the development of production techniques, so that the electric field in each component of the LSI tends to be high. Therefore, a high electric field occurring in the vicinity of a drain of MOS transistor causes impact ionization of carriers, so that hot carriers having high energy are likely to be generated. The hot carriers cause damage to a gate oxide film, and thus causes aging changes in the threshold voltage or the drain current of a transistor over time, that is, property deterioration. Consequently, this may change the operation frequency property or the like of the LSI, which is an assembly of the transistors, and finally may cause malfunction to the LSI. Therefore, in the design of the LSIs, it is essential to ensure the reliability in accordance with a desired lifetime of the product, so that in general, a design tolerance for deterioration of the LSI, that is, an aging deterioration margin amount is included.
More specifically, the signal path delay shown in the equation (1) is not constant throughout the elapse of the operation time of the LSI, but is changed by the hot carrier phenomenon or the like. The degree of the delay change due to the hot carrier phenomenon depends on the type of the circuit, the operating conditions of the circuit (e.g., the supply voltage, the temperature, the number of switching operations, the slew rate of an input signal, whether a signal transition is to go high or low, and an output signal load or the like), and the production deviation of the circuit properties, and usually is increased. Taking this aging deterioration into account, it is not sufficient to satisfy the equation (1) and it is necessary to satisfy the following equation (3) in order to guarantee the operation throughout the product lifetime of the LSI.
t cyclexe2x89xa7xcexa3(ti+xcex94ti)+K(i=1 to N)xe2x80x83xe2x80x83(3) 
where xcexa3 xcex94ti is a variation amount of the signal path delay due to deterioration. Thus, when designing a LSI, it is necessary to make allowance for the influence of delay increments due to deterioration, and to include a design tolerance, that is, an aging deterioration margin amount so that the equation (3) is satisfied.
If the aging deterioration margin amount included at the time of the design of the LSI is too small, the reliability is not sufficient so that a malfunction may be caused before the desired product lifetime expires in the future. On the other hand, if the aging deterioration margin amount is too large, the reliability is excessive. In general, the reliability and the performance of the LSI has a trade-off relationship, so that excessive reliability results in degraded performance (e.g., operation frequency) of the LSI. Therefore, when a suitable aging deterioration margin amount cannot be set, it is difficult to develop LSIs for which both high performance and reliability are required, such as microprocessors.
Examples of a method of testing the design of a LSI with making an allowance for aging deterioration as described above include a method described in U.S. Pat. No. 5,634,001. In this method, a LSI is designed by using the simulation technique disclosed in U.S. Pat. No. 5,533,197 to predict the operation timing property of the LSI after the operation for the desired product lifetime, that is, all the signal path delays after deterioration of the LSI shown in equation (3), based on the design information of the LSI in the design process, and confirming with simulations that the delay after deterioration of the most delayed signal path (critical path) is within the cycle time. In this manner, it is attempted to include neither too much nor too little aging deterioration margin amount.
However, the method for predicting all the signal path delays after deterioration of the LSI with the simulation technique as described above results in a large amount of calculations, so that calculation takes much time, and a large scale apparatus is required.
On the other hand, similarly to the margin amount before deterioration described with reference to equation (2), it is conceivable to easily obtain the aging deterioration margin amount for allowance for aging deterioration with the derating factors. In such a case, it is necessary to set suitable values for the derating factors. However, the magnitude of such derating factors is affected by various more factors such as the type of the circuit, the history of the operating conditions, the deviation in the deterioration degree, than that of the derating factors for obtaining the margin amount before deterioration. Therefore, such derating factors cannot be obtained easily. In the conventional designing method described in the above U.S. Patent, the worst delays both before and after deterioration in all the signal paths are obtained directly by simulations at the time of the design of the LSI, and therefore applying this method to the design method using the derating factors based on equation (2) is not taken into account.
The aging deterioration margin amount is required to be included, not only in the design stage of the LSI, but also in inspection in the production stage. More specifically, in order to guarantee the desired product lifetime of a LSI (e.g., 10 years), it is necessary not only to test whether or not the LSI can operate normally at a time before deterioration, that is, immediately after the production of the LSI (before going to the market), but also to check whether or not the LSI can operate normally over the period of time of the production lifetime, that is, whether or not the aging deterioration margin amount is sufficient and is not excessive. For such checking, a technique for inspecting LSIs with a voltage lower than the supply voltage that guarantees the operation, such as described in U.S. Pat. No. 5,634,001, is known.
More specifically, the LSI operable cycle time depends on the supply voltage. As shown by the solid line in FIG. 2, when the supply voltage is high, the operable cycle time is short (the operable frequency is high), and when the supply voltage is low, the operable cycle time is long (the operable frequency is low). When the signal path delay is deteriorated as aging, the relationship between the supply voltage and the operable cycle time is as shown by the broken line in FIG. 2. In other words, for example, when the same supply voltage is applied before and after deterioration, the operable cycle time after deterioration is longer than before deterioration.
First, with respect to a targeted LSI, the relationship between the supply voltage and the operable cycle time (solid line in FIG. 2) before aging deterioration (beginning-of-life) is obtained by actual measurement. In addition, a delay t BOL at the path (critical path) having the largest signal path delay before aging deterioration and a delay t EOL at the critical path after aging deterioration (after a continuous operation for the desired production lifetime: end-of-life) are obtained by aging simulations. Then, based on these values, supply voltages V BOL and V EOL that allow operation at the cycle times corresponding to the delays t BOL and t EOL, respectively, of the LSI before aging deterioration are obtained, and the difference xcex94V=V BOLxe2x88x92V EOL is calculated. Then, a voltage (VDDminxe2x88x92xcex94V) lower by the difference xcex94V than the operation guarantee minimum voltage VDD min is applied to the LSI before deterioration, and when the LSI operates at the cycle time corresponding to the delay t BOL under the voltage (VDDminxe2x88x92xcex94V), the LSI is determined to be non-defective. When the LSI does not operate, the LSI is determined to be defective. In other words, it is estimated whether or not the LSI is operable after aging deterioration by converting an increment xcex94t=t EOLxe2x88x92t BOL of the delays before and after aging deterioration to the difference xcex94V between the supply voltages.
However, the method for inspecting LSIs using the supply voltage difference xcex94V obtained by actual measurement after production of the targeted LSI has the following problems. As shown in FIG. 3, assuming that a signal path A is the critical path in a fresh LSI, based on that path, apparently, it is possible to obtain the supply voltage difference xcex94V by simulations and actual measurement as above, and to check an apparent delay increment xcex94t corresponding to the aging deterioration of the signal path A by controlling the supply voltage based on the difference. (Therefore, in the method of the above reference, an LSI in the initial state is inspected not by using VDD min as the supply voltage as shown in (1) of FIG. 3, but by reducing to (VDD minxe2x88x92xcex94V) to increase the delay as shown in (2) of FIG. 3 so that the delay after deterioration of (3) of FIG. 3 is simulated.) However, in reality, the relationship between the supply voltage and the delay and the relationship between the operation time and the delay are non-linear, and these relationships are different between signal paths. Therefore, even if a LSI is determined to be non-defective in an inspection with the supply voltage difference xcex94V set at the signal path A, the LSI does not necessarily operate normally during deterioration, and the opposite case can be true. More specifically, with respect to another signal path B that has the same signal path delay as that of the signal path A at a supply voltage VDD min in the initial state as shown in (4) of FIG. 3, even if in an inspection with the supply voltage (VDD minxe2x80x94xcex94V) as shown in (5) of FIG. 3, the delay is within a design targeted delay so that it is determined that there is no problem, there is a possibility that the delay after deterioration in reality is beyond the design targeted delay, resulting in the malfunction, as shown in (6) of FIG. 3.
As described above, the conventional design method for LSIs has the problem that the aging margin amount including an allowance for aging deterioration cannot be obtained easily. Furthermore, in the method of inspecting with adjusting the supply voltage at the inspection to check whether or not the aging margin amount is sufficient and not excessive, that is, the inspection method of inspecting with setting the supply voltage to be low, the actually deteriorated properties of the circuits cannot be reflected, so that there is a possibility that an appropriate inspection cannot be performed.
Therefore, with the foregoing problems in mind, it is an object of the present invention to provide an apparatus and a method for calculating an aging deterioration margin amount of LSIs and that allow an aging deterioration margin amount including an allowance for aging deterioration to be obtained easily, for example, with derating factors. Furthermore, it is another object of the present invention to provide an inspection method for LSIs that allows appropriate inspection including an allowance for aging deterioration.
In order to achieve the above objects, the present invention is directed to an apparatus for calculating an aging deterioration margin amount of a LSI for calculating an aging deterioration margin amount to be included as a design tolerance with respect to a property of the LSI so that the LSI can operate even if the property deteriorates. The apparatus includes beginning-of-life property generating means for obtaining a property before deterioration of the property in an initial state of the LSI with respect to at least a part of a plurality of signal paths constituting the LSI; end-of-life property generating means for obtaining a property after deterioration of the property when a predetermined operation period has passed under a predetermined operating condition with respect to at least a part of a plurality of signal paths constituting the LSI; property deterioration degree generating means for obtaining a property deterioration degree which is a ratio of the property after deterioration to the property before deterioration in a signal path having a smallest tolerance of the property after deterioration with respect to a property necessary for the LSI to operate of the plurality of signal paths; and aging deterioration margin amount generating means for substantially obtaining an aging deterioration margin amount based on the property before deterioration and the property deterioration degree.
Thus, in general, the property before deterioration can be obtained comparatively easily, compared with the property after deterioration. Therefore, if the property deterioration degree of a certain LSI is obtained, an aging deterioration margin amount can easily be obtained without obtaining the property after deterioration every time for other LSIs or the like. The aging deterioration margin amount may be obtained, not only for other LSIs, but also for the same LSI that has been subjected to design change, or other signal paths of the same LSI for which the property after deterioration has not been obtained. Herein, the actually obtained value is not necessarily the aging deterioration margin itself, but can be in the form matched with the design circumstances using the value, such as the total of the property amount used as the reference and the aging deterioration margin amount, or the inverse number thereof. As long as the value substantially includes the information of the aging deterioration margin amount as described above, the present invention can be applied thereto and the same effects are provided.
Furthermore, a predetermined tolerance may be included in the aging deterioration margin amount obtained in the above-described manner. In other words, the aging deterioration amount can be increased or decreased, for example, to enhance the reliability with respect to the influence of the factors that are difficult to take into account when obtaining the property after deterioration, or to broaden the tolerance range of the reliability (to allow a reduction of the reliability to some extent).
Furthermore, the property after deterioration is not necessarily obtained for all signal paths, but may be obtained for a group of signal paths having a small tolerance of the property before deterioration with respect to the property necessary for the LSI to operate of a plurality of groups into which a plurality of signal paths constituting the LSI are divided. In other words, the property after deterioration is obtained only for the signal paths whose property after deterioration has high possibility of being used to obtain the property deterioration degree, and is not obtained for signal paths having a sufficient tolerance for the property before deterioration, and thus the computation amount is reduced and the processing efficiency of the entire apparatus can be increased.
Furthermore, the present invention can be applied to, for example, signal path delays. In this case, if the property deterioration degree is used as a derating factor corresponding to aging deterioration of the property and the delay before deterioration is multiplied by derating factors corresponding to each of at least a product deviation, a supply voltage variation, and a temperature variation as well as the derating factor corresponding to aging deterioration, the largest delay including the aging deterioration margin amount can be calculated easily.
Furthermore, the reliability of the LSI can be enhanced in the following manner. The supply voltage condition in the predetermined operating conditions when the end-of-life property generating means obtains the property after deterioration is different from a supply voltage condition under which the beginning-of-life property generating means and the end-of-life property generating means obtain the property before deterioration and the property after deterioration. Alternatively, the beginning-of-life property generating means and the end-of-life property generating means obtain the delay before deterioration and the delay after deterioration, using the property of the element whose delay before deterioration and delay after deterioration are largest (for example, the lowest responsibility of the element) in the range of the property deviation of elements constituting the LSI.
Furthermore, the apparatus for calculating an aging deterioration margin amount can be configured so as to include an aging deterioration margin amount generating means for substantially obtaining an aging deterioration margin amount, apart from the apparatus for obtaining the property deterioration degree as described above. In this case, it is not necessary that the apparatus has a function to obtain the property after deterioration to obtain the property deterioration degree, and therefore the aging deterioration margin can be obtained with a small-scale apparatus.
Furthermore, by inspecting the operation of the LSI, using the frequency obtained by multiplying the property deterioration degree obtained in the same manner as the aging deterioration margin amount as above by a predetermined frequency as the operation frequency, errors due to a non-linear relationship between the supply voltage and the delay cannot occur, for example, compared with the case where inspection is performed with the reduced supply voltage obtained by converting the difference between delays before and after deterioration to a supply voltage difference. Thus, underestimate or overestimate of the aging deterioration margin amount can be avoided without fail.